systemverilog code
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systemverilog design
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systemverilog module
Simplified Chinese_translation
systemverilog testbench
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systemverilog verification
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systemverilog interface
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systemverilog task
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systemverilog function
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systemverilog package
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systemverilog constraint
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the systemverilog syntax supports advanced data types.
SystemVerilog语法支持高级数据类型。
i wrote a comprehensive systemverilog testbench for the design.
我为该设计编写了一个全面的SystemVerilog测试平台。
the systemverilog simulation ran successfully on the server.
SystemVerilog仿真在服务器上成功运行。
we instantiated the systemverilog module in the top-level design.
我们在顶层设计中实例化了SystemVerilog模块。
the systemverilog interface simplifies the communication between blocks.
SystemVerilog接口简化了模块间的通信。
systemverilog assertions helped catch the timing violation.
SystemVerilog断言帮助检测到了时序违规。
the systemverilog class encapsulates the transaction logic.
SystemVerilog类封装了事务逻辑。
systemverilog uvm provides a standard verification methodology.
SystemVerilog UVM提供了一种标准的验证方法学。
the systemverilog dpi allows interaction with c functions.
SystemVerilog DPI允许与C函数进行交互。
the synthesis tool supports systemverilog constructs.
综合工具支持SystemVerilog结构。
systemverilog enum types improve code readability.
SystemVerilog枚举类型提高了代码的可读性。
the systemverilog always_ff block ensures proper flip-flop inference.
SystemVerilog always_ff块确保了正确的触发器推断。
systemverilog code
Simplified Chinese_translation
systemverilog design
Simplified Chinese_translation
systemverilog module
Simplified Chinese_translation
systemverilog testbench
Simplified Chinese_translation
systemverilog verification
Simplified Chinese_translation
systemverilog interface
Simplified Chinese_translation
systemverilog task
Simplified Chinese_translation
systemverilog function
Simplified Chinese_translation
systemverilog package
Simplified Chinese_translation
systemverilog constraint
Simplified Chinese_translation
the systemverilog syntax supports advanced data types.
SystemVerilog语法支持高级数据类型。
i wrote a comprehensive systemverilog testbench for the design.
我为该设计编写了一个全面的SystemVerilog测试平台。
the systemverilog simulation ran successfully on the server.
SystemVerilog仿真在服务器上成功运行。
we instantiated the systemverilog module in the top-level design.
我们在顶层设计中实例化了SystemVerilog模块。
the systemverilog interface simplifies the communication between blocks.
SystemVerilog接口简化了模块间的通信。
systemverilog assertions helped catch the timing violation.
SystemVerilog断言帮助检测到了时序违规。
the systemverilog class encapsulates the transaction logic.
SystemVerilog类封装了事务逻辑。
systemverilog uvm provides a standard verification methodology.
SystemVerilog UVM提供了一种标准的验证方法学。
the systemverilog dpi allows interaction with c functions.
SystemVerilog DPI允许与C函数进行交互。
the synthesis tool supports systemverilog constructs.
综合工具支持SystemVerilog结构。
systemverilog enum types improve code readability.
SystemVerilog枚举类型提高了代码的可读性。
the systemverilog always_ff block ensures proper flip-flop inference.
SystemVerilog always_ff块确保了正确的触发器推断。
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